FIG. 1 shows a block diagram of a typical display driver 100, such as for a LCD (liquid crystal display) panel 102, operating in a video interface mode. Components, such as the LCD panel 102, a CPU 104, and a graphic processor 106, that are not part of the display driver 100 in FIG. 1 are shown outlined in dashed lines. The display driver 100 operates in a video interface mode for processing video data resulting in moving images on the LCD panel 102.
For the video interface mode, the CPU 104, which is a data processing unit, sends control signals (CTRLS) to a graphic processor 106 indicating that the graphic processor 106 is to process video data. The graphic processor 106 then sends such video data (VIDEO_DATA), a system clock (DOTCLK), and synchronization signals (H_SYNC and V_SYNC) to a timing controller 108 of the display driver 100.
The display driver 100 includes the timing controller 108, an oscillator 110, a voltage controller 112, a data line driver 114, a scan line driver 116, and a common voltage (VCOM) generator 118. The timing controller 108 uses the VIDEO_DATA, DOTCLK, and H_SYNC signals from the graphic processor 106 to generate synchronized S_DATA signals for the data line driver 114 to control timing of data line signals generated from the data line driver 114 and applied on data lines S1, S2, . . . , and Sm of the LCD panel 102.
Similarly, the timing controller 108 uses the DOTCLK and V_SYNC signals from the graphic processor 106 to generate gate signals for the scan line driver 115 to control timing of gate line signals generated from the scan line driver 116 and applied on gate lines G1, G2, . . . , and Gn of the LCD panel 102. Furthermore, the timing controller 108 uses the DOTCLK signal from the graphic processor 106 to generate an initial common voltage (VCOM′) signal for the VCOM generator 118 to control timing of a common voltage (VCOM) signal generated from the VCOM generator 118 and applied on a common node of the LCD panel 102.
The voltage controller 112 includes at least one charge pump for generating at least one DC voltage. A typical charge pump used in a display driver generates a DC voltage that is a multiple of a reference voltage (Vref) when pumped by a charge pumping signal (DCCLK). Examples of such charge pumps in the prior art are disclosed in U.S. Patent Application Publication No. US 2003/0011586 to Nakajima and U.S. Patent Application Publication No. US 2002/0044118 to Sekido et al.
At least one DC voltage (DCV1) is generated by the voltage controller 112 for the data line driver 114 to control the magnitude of the respective data line signal applied on each of the data lines S1, S2, . . . , and Sm. Similarly, at least one DC voltage (DCV2) is generated by the voltage controller 112 for the scan line driver 116 to control the magnitude of the respective gate line signal applied on each of gate lines G1, G2, . . . , and Gn. Furthermore, a DC voltage (DCV3) is generated by the voltage controller 112 for the VCOM generator 118 to control the magnitude of the VCOM signal applied on the common node of the LCD panel 102.
The timing controller 108 generates the Vref used by the at least one charge pump within the voltage controller 112 such that the timing controller 108 controls the magnitude of the driving signals applied on the LDC panel 102. The driving signals applied on the LCD panel 102 include the respective data line signal applied on each of the data lines S1, S2, . . . , and Sm, the respective gate line signal applied on each of gate lines G1, G2, . . . , and Gn, and the VCOM signal applied on the common node of the LCD panel 102.
An oscillator 110 is used to generate the charge pumping signal (DCCLK) that pumps the at least one charge pump within the voltage controller 112 to generate the DC voltages DCV1, DCV2, and DCV3. In this manner, the display driver 100 processes the VIDEO_DATA, DOTCLK, H_SYNC, and V_SYNC signals from the graphic processor 106 to generate the driving signals applied on the LCD panel 102 to create moving images on the LCD panel 102 in a video interface mode. Such operations and such components 108, 110, 112, 114, 116, and 118 of the display driver 100 in FIG. 1 are known to one of ordinary skill in the art.
Referring to FIG. 2, another display driver 120 is configured to operate in a CPU interface mode for processing data resulting in a still image on the LCD panel 102. Elements having the same reference number in FIGS. 1 and 2 refer to elements having similar structure and function. A timing controller 122 of the display driver 120 operating in the CPU interface mode is directly coupled to the CPU 104. The timing controller 122 receives the image data directly from the CPU 104 in the CPU interface mode.
The timing controller 122 then uses an oscillator clock (OSC_CLK) signal generated from the oscillator 110 for synchronizing the driving signals applied on the LCD panel 102. The driving signals applied on the LCD panel 102 include the respective data line signal applied on each of the data lines S1, S2, . . . , and Sm, the respective gate line signal applied on each of gate lines G1, G2, . . . , and Gn, and the VCOM signal applied on the common node of the LCD panel 102. Such operations and such components 122, 110, 112, 114, 116, and 118 of the display driver 120 in FIG. 2 are known to one of ordinary skill in the art.
FIG. 3 shows a timing diagram of signals during operation of the display driver 120 of FIG. 2 in the CPU interface mode. Referring to FIG. 3, the OSC_CLK signal 132 and the charge pumping (DCCLK) signal 134 are synchronized to each other. Thus, each of the falling transition 136 and the rising transition 138 of the DCCLK signal 134 is synchronized to a rising edge of the OSC_CLK signal 132.
In addition, for the CPU interface mode in FIG. 3, the driving signals, such as the VCOM signal 140 for example, applied on the LCD panel 102 are also synchronized to the OSC_CLK signal 132. Thus, each of the falling transition 142 and the rising transition 144 of the VCOM signal 140 is synchronized to a rising edge of the OSC_CLK signal 132. The VCOM signal 140 in FIG. 3 is an ideal waveform without any noise imposed thereon. FIG. 3 also shows a realistic VCOM signal 146 with noise waveforms super-imposed on the ideal VCOM signal waveform.
The charge pumping (DCCLK) signal 134 is used to generate the DCV3 voltage that determines the magnitude of the VCOM signal 146. The DCCLK signal 134 is synchronized to the OSC_CLK signal 132 and is typically generated from the OSC_CLK signal 132. For example, a frequency divider is used to generate the DCCLK signal 134 having a period that is an integer multiple of the period of the OSC_CLK signal 132.
Because the DCCLK signal 134 is derived from the OSC_CLK signal 132, the noise waveform of the VCOM signal 146 is synchronized to half-periods of the OSC_CLK signal 132. In addition, because the VCOM signal 146 is also synchronized to OSC_CLK signal 132 in the CPU interface mode, the noise waveform of the VCOM signal 146 has a regular pattern across the periods of the VCOM signal 146. Thus, such regular noise applied on the LCD panel 102 causes a uniform affect repeated across the whole LCD panel 102. Such a uniform affect on the image repeated across the whole LCD panel 102 from regular noise is not noticeable to the human eye in the CPU interface mode.
FIG. 4 shows a timing diagram of signals during operation of the display driver 100 of FIG. 1 in the video interface mode. Similar to the CPU interface mode, the charge pumping (DCCLK) signal 134 is synchronized to the OSC_CLK signal 132 generated from the oscillator 110. However, for the video interface mode in FIG. 4, the driving signals, such as the VCOM signal 154, applied on the LCD panel 102 are synchronized to the system clock (DOTCLK) signal 152 from the graphic processor 106. Thus, each of the falling transition 156 and the rising transition 158 of the VCOM signal 154 is synchronized to a rising edge of the DOTCLK signal 152.
The VCOM signal 154 in FIG. 4 is an ideal waveform without any noise imposed thereon. FIG. 4 also shows a realistic VCOM signal 160 with noise waveforms super-imposed on the ideal VCOM signal waveform. The VCOM signal 160 is synchronized to the DOTCLK signal 152 that is from a different clock source 106 than the oscillator 110 that generates the OSC_CLK 132 signal. Thus, the VCOM signal 160 is not synchronized to the OSC_CLK 132 signal and the charge pumping (DCCLK) signal 134.
As a result, the noise generated from the at least charge pump does not have a regular pattern across the VCOM signal 160. The noise is particularly irregular at any falling transition 162 and any rising transition 164 of the VCOM signal 160. Such irregular noise creates non-uniform affects on the image across the LCD panel 102, and such non-uniform noise applied on the LCD panel 102 is noticeable to the human eye.
A display driver that creates images on the LDC panel 102 without such noticeable affects from noise is desired for both the CPU and video interface modes of operation. In addition, a display driver capable of operating in both the CPU and video interface modes of operation as dictated by the CPU is desired.